The present invention generally relates to the field of analog-to-digital converters (xe2x80x9cADCxe2x80x9d). More specifically, the present invention relates to multi-bit quantizers in sigma-delta modulators.
A primary advantage of continuous-time sigma-delta ADC devices over discrete-time multi-bit sigma-delta ADC devices is reduced power dissipation. At the same time, a primary advantage of discrete-time multi-bit sigma-delta ADC devices over single-bit sigma-delta ADC devices is the increased resolution that can be achieved at lower sampling rates. As such, there is motivation in the art to apply multi-bit quantizer technology to a continuous-time sigma-delta ADC structure. However, multi-bit quantizer technology can be expensive in terms of power consumption and circuit area when applied to sigma-delta ADC devices. The reason for this is that multi-bit quantizers are made up of banks of low offset comparators, while a single-bit sigma delta ADC device requires only a single comparator with a non-critical offset specification. The power penalty is most significant in the context of continuous-time sigma-delta ADC devices, because the primary motivation for implementing a continuous-time sigma-delta ADC device is to reduce power.
The present invention advances the art by a contribution of a novel multi-bit continuous-time sigma-delta ADC structure that addresses the aforementioned power penalty associated with a multi-bit quantizer.
The present invention is an analog-to-digital converter comprising a summing module, a voltage controlled oscillating module, a dynamic element matching module and a feedback module. In a base form, the summing module is operated to provide an analog summation signal indicative of a summation of an analog input signal and an analog feedback signal. The voltage controlled oscillating module is operated to provide a first set of bits as a digital representation of the analog summation signal. The dynamic element matching module is operated to provide a second set of bits as a digital representation of a periodic sampling of the first set of bits. And, the feedback module is operated to provide the analog feedback signal as an analog representation of the second set of bits.